This application claims the priority benefit of Taiwan application serial no. 87117296, filed Oct. 20, 1998, the full disclosure of which is incorporated herein by reference.
1. Field of the Invention
The invention relates to an input/output (I/O) control device, and in particular to an input/output control device used to enhance the efficiency of accessing input/output devices in a computer system.
2. Field of the Related Art
Due to great progress in the semiconductor technology, computer, an indispensable apparatus, has been widely used in out daily life.
Referring to FIG. 1, a general personal computer is presented. In FIG. 1, a computer system 100 includes a central processing unit (CPU) 110, a chipset 120, a memory 130 and a plurality of input/output (I/O) devices 151-15N electrically connected to a bus 140.
It is well-known that the CPU 110, a heart of the computer system 100, is responsible for all operations. Most control circuits in the computer system 100 all are integrated in the chipset 120 except for the CPU 110. The chipset 120 is used to control the communications between the CPU 110 and other devices, such as accesses to the memory 130 or the I/O devices 151-15N. The memory 130 can be used to store programs and data provided to the CPU 110 for operations. The I/O devices 151-15N, such as hard disk for store a great amount of data, printer, mouse, keyboard, scanner and the like, are electrically connect to the CPU 110 via the chipset 120.
In an ordinary computer system, the access speed of a memory is faster then those of I/O devices. In addition, the I/O devices electrically connected to the same computer system are various and have different access speeds. To handle the I/O devices with different access speeds, the CPU separately executes instructions for the accesses to the memory and the I/O devices.
In an early adopted method as shown in FIG. 1, the CPU 110 has a first input terminal for receiving a ready signal RDY. When the CPU 110 accesses an I/O device, the I/O device can inform the CPU 110 with the ready signal RDY that data required by the CPU 110 is ready or the I/O device has received data from the CPU 110. Thus, the CPU 110 can communicate well with the I/O devices having different access speeds.
Furthermore, in line with great progress in the semiconductor technology, a large number of devices has been contained in a single chip, resulting in more complicated functions and a higher speed of a CPU. For example, with pipeline technique, a CPU almost can execute an instruction within one clock cycle, or a form of branch predication is used to previously determine a flow of program execution. Moreover, refreshing the program codes and data of a pipeline help speed up the operation speed of the CPU. On the other hand, a multi-thread, multi-task operating system can completely function well because the capability of hardware operations is enhanced. Therefore, several tens of processes can be concurrently executed in turn in a short time by completely using the capability provided by the hardware.
Although the operation capability and speed of a CPU are greatly increased, the access speeds of I/O devices has not increased yet. Therefore, only using the ready signal RDY to control the accesses to the I/O devices could result in a lower efficiency for the entire computer system if the access speeds of the I/O devices are slower. As shown in FIG. 1, to overcome this problem, the CPU 110 further provides a second input terminal for receiving a defer signal DEFER. When an I/O device being accessed by the CPU 110 has a lower access speed, the I/O device can transmit the defer signal DEFER instead of the ready signal RDY in response to the CUP 110 after receiving a control instruction from the CPU 110. Following receiving the defer signal DEFER by the CPU 110, the CPU 110 does not execute any instruction associated with the I/O device temporarily. Instead, the CPU executes other instructions independent of the I/O device. After a default time, the CPU 110 continuously proceeds an instruction associated with the I/O device. If the I/O device can not complete an operation requested by the CPU 110, a corresponding defer signal DEFER is again transmitted to the CPU 110 within the default time to inform that the I/O device has not completed the requested operation yet. The defer signal DEFER is maintained until the I/O device already completes the requested operation. However, if the CPU 110 does not receive another defer signal DEFER within the default time after the previous defer signal DEFER, it shows that the I/O device has completed a data access.
Moreover, in the computer system 100, the CPU 110 communicates with the I/O devices 151-15N via the chipset 120. When the CPU 110 transmits/receives data to/from one of the I/O devices 151-15N, the chipset 120 sends out a corresponding ready signal RDY or defer signal DEFER according to the access speed of the I/O device. In practical, it takes more time to send the defer signal DEFER in response to the CPU 110. For example, Intel Pentium II CPU takes 6 clock cycles to handle the defer signal DEFER in a form of complicated control. Every period of time, the CPU repeats the same operation. To overcome this problem, in the prior art, when the CPU 110 accesses an I/O device, the chipset 120 first transmits a ready signal DRY to the CPU for response. If the I/O device to communicate with the CPU 110 has not completed an appointed operation yet within a default time, the chipset 120 sends a defer signal DEFER in response to the CPU until the I/O device already completes the appointed operation.
As can be obviously seen from the above, the chipset 120 first sends a ready signal RDY in response to the CPU, regardless of the access speed of the I/O device being accessed by the CPU. After a default time, the chipset 120 sends a defer signal DEFER to the CPU 110 instead of a ready signal RDY Of course, the CPU does not take much time for standby, if the I/O device accessed by the CPU completes a data access within the default time. However, if the accessed I/O device can not complete the data access within the default time, the chipset 120 alternatively sends a defer signal DEFER in response to the CPU. In this case, the CPU 110 vainly wastes the standby time before receiving the defer signal DEFER, leading to a low efficiency for the entire computer system.
In view of the above, an object of the invention is to provide an input/output (I/O) control device with a means for storing a mapping table which contains pairs of address and response time associated with the I/O devices, respectively. When a CPU accesses one of the I/O devices, the I/O control device responds the CPU with a ready signal RDY or a defer signal DEFER according to the response time of the I/O device, thereby reducing the standby time of the CPU and increasing the efficiency of the entire computer system.
To achieve the above-stated object, the I/O control device used to control the accesses to a plurality of input/output devices by a central processing unit (CPU) in a computer system, comprises a means for storing a mapping table containing pairs of address and response time data associated with the input/output devices, respectively. When an input/output device is accessed by the central processing unit, the input/output control device locates a corresponding response time from the mapping table according to an address of the accessed input/output device. If the located response time is more than a default time, the input/output control device defers a communication between the central processing unit and the input/output device in a form of defer control. Inversely, if the located response time is less than the default time, the input/output control device builds a communication between the central processing unit and the input/output device in a form of general control.